Apparatuses and methods to selectively perform logical operations

ABSTRACT

The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

PRIORITY INFORMATION

This application is a Continuation of U.S. application Ser. No.15/298,798, filed Oct. 20, 2016, which issues as U.S. Pat. No. 9,805,772on Oct. 31, 2017, the contents of which are included herein byreference.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory andmethods, and more particularly, to apparatuses and methods related toselectively performing logical operations.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits in computing systems. There are many different typesof memory including volatile and non-volatile memory. Volatile memorycan require power to maintain its data (e.g., host data, error data,etc.) and includes random access memory (RAM), dynamic random accessmemory (DRAM), static random access memory (SRAM), synchronous dynamicrandom access memory (SDRAM), and thyristor random access memory (TRAM),among others. Non-volatile memory can provide persistent data byretaining stored data when not powered and can include NAND flashmemory, NOR flash memory, and resistance variable memory such as phasechange random access memory (PCRAM), resistive random access memory(RRAM), and magnetoresistive random access memory (MRAM), such as spintorque transfer random access memory (STT RAM), among others.

Computing systems often include a number of processing resources (e.g.,one or more processors), which may retrieve and execute instructions andstore the results of the executed instructions to a suitable location. Aprocessing resource can comprise a number of functional units such asarithmetic logic unit (ALU) circuitry, floating point unit (FPU)circuitry, and a combinatorial logic block, for example, which can beused to execute instructions by performing logical operations such asAND, OR, NOT, NAND, NOR, and XOR, and invert (e.g., inversion) logicaloperations on data (e.g., one or more operands). For example, functionalunit circuitry may be used to perform arithmetic operations such asaddition, subtraction, multiplication, and division on operands via anumber of logical operations.

A number of components in a computing system may be involved inproviding instructions to the functional unit circuitry for execution.The instructions may be executed, for instance, by a processing resourcesuch as a controller and/or host processor. Data (e.g., the operands onwhich the instructions will be executed) may be stored in a memory arraythat is accessible by the functional unit circuitry. The instructionsand data may be retrieved from the memory array and sequenced and/orbuffered before the functional unit circuitry begins to executeinstructions on the data. Furthermore, as different types of operationsmay be executed in one or multiple clock cycles through the functionalunit circuitry, intermediate results of the instructions and data mayalso be sequenced and/or buffered.

In many instances, the processing resources (e.g., processor and/orassociated functional unit circuitry) may be external to the memoryarray, and data is accessed via a bus between the processing resourcesand the memory array to execute a set of instructions. Processingperformance may be improved in a processing-in-memory (PIM) device, inwhich a processing resource may be implemented internal and/or near to amemory (e.g., directly on a same chip as the memory array). A PIM devicemay reduce time in processing and may also conserve power. Data movementbetween and within arrays and/or subarrays of various memory devices,such as PIM devices, can affect processing time and/or powerconsumption.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an apparatus in the form of a computingsystem including a memory device in accordance with a number ofembodiments of the present disclosure.

FIG. 2 is a schematic diagram of a portion of a memory array includingsensing circuitry in accordance with a number of embodiments of thepresent disclosure.

FIG. 3 is a schematic diagram illustrating a portion of a memory arrayincluding compute component comprising selection logic circuitry andcompute component storage location(s)/shift logic circuitry inaccordance with a number of embodiments of the present disclosure.

FIG. 4 is another schematic diagram illustrating a portion of a memoryarray including compute component comprising selection logic circuitryand compute component storage location(s)/shift logic circuitry inaccordance with a number of embodiments of the present disclosure.

FIG. 5 is another schematic diagram illustrating a portion of a memoryarray including compute component comprising selection logic circuitryand compute component storage location(s)/shift logic circuitry inaccordance with a number of embodiments of the present disclosure.

FIG. 6 is a schematic diagram illustrating sensing circuitry inaccordance with a number of embodiments of the present disclosure.

FIG. 7A is a logic table illustrating selectable logical operationresults implemented by sensing circuitry in accordance with a number ofembodiments of the present disclosure.

FIG. 7B is another logic table illustrating selectable logical operationresults implemented by sensing circuitry in accordance with a number ofembodiments of the present disclosure.

FIG. 8 is a table illustrating selective performance of a logicaloperation in accordance with a number of embodiments of the presentdisclosure.

FIG. 9 is a timing diagram for performing a selected logical operationin accordance with a number of embodiments of the present disclosure.

FIG. 10 illustrates an example configuration of sensing circuitry inaccordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods related toperforming masking of logical operations. An example apparatus comprisessensing circuitry including a sense amplifier and a compute component. Acontroller is coupled to the sensing circuitry and is configured tocause storing of an indication of whether a logical operation is to beselectively performed between an operand stored in the sensing circuitryand an operand stored in the sense amplifier. As used herein, “sensingcircuitry” includes a sense amplifier and a compute component. In someembodiments, sensing circuitry may include one or more storage locationsassociated therewith. For example, sensing circuitry may include one ormore latches configured to store a data value (e.g., an operand). In anumber of embodiments, compute component circuitry may include one ormore storage locations (e.g., compute component storage locations)associated therewith. For example, compute component circuitry mayinclude one or more latches configured to store an operand (e.g., a datavalue which may serve as an input to a logical operation). As describedfurther herein, the sensing circuitry can be formed on pitch with senselines (e.g., digit lines) of an array.

In a number of embodiments, sensing circuitry coupled to respectivecolumns of an array can be referred to as sensing components (e.g., witheach sensing component comprising a sense amplifier and correspondingcompute component). The sensing components can be controlled to performvarious operations (e.g., logical operations) on a per column basis. Forinstance, in a number of embodiments, the sensing componentscorresponding to respect columns (e.g., pairs of complementary digitlines) can serve as respective processing resources (e.g, 1-bitprocessing elements). A number of embodiments of the present disclosurecan provide benefits such as restricting (e.g., masking) particularlogical operations comprising a logical computation to a selected groupof bits in the memory device to limit power consumption and/or an amountof time consumed in performing logical operations be selectivelyperforming such logical operations. In some embodiments, selectivelyperforming logical operations may reduce a number of row operationsassociated with performing a logical operation, which may increaseperformance and/or efficiency of the memory device.

Some approaches to performing logical operations in a memory device caninclude performing multiple row cycles to perform logical operations.For example, in some approaches, multiple row cycles may be used toperform operations (e.g., Boolean logical operations) by transferring amask, operand, and/or resultant data between rows of a memory device. Asused herein, a “mask” is one or more data values that provide anindication of whether a logical operation is to be performed between afirst operand stored in sensing circuitry and a second operand stored insensing circuitry.

In contrast, embodiments of the present disclosure include providingdedicated circuitry in the sensing components to store logical operationmasking data locally, which can reduce the number of row cyclesassociated with some approaches to logical operation masking. In someembodiments, the dedicated circuitry may be provided such that an impactto the size of the die is minimized.

In some embodiments, a sensing component may be connected to anothersensing component such that data values (e.g., bits) may be moved (e.g.,shifted) from one sensing component to another sensing component.Shifting data values between one sensing component and another sensingcomponent may be done synchronously such that a first sensing componentreceives a data value from a second sensing component as the secondsensing component passes its data value to a third sensing component. Insome embodiments, shifting data between sensing components canfacilitate various processing functions such as the multiplication,addition, etc. of two data values (e.g., operands).

In some approaches, data values that are used as operands to performlogical operations in sensing circuitry have been stored using a dynamiccapacitance associated with a latch on which the data value is stored.Embodiments of the present disclosure may alleviate lost charge, leakedcharge, and/or charge coupling, which may affect storing data valuesusing dynamic capacitance, by providing one or more active storagelocations (e.g., static latches). For example, some embodiments canallow for selectively performing logical operations in sensing circuitrywithout depending upon (or relying on) dynamic capacitance, and insteadmay allow for data values to be actively held (e.g., latched).

In the following detailed description of the present disclosure,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration how one or more embodimentsof the disclosure may be practiced. These embodiments are described insufficient detail to enable those of ordinary skill in the art topractice the embodiments of this disclosure, and it is to be understoodthat other embodiments may be utilized and that process, electrical,and/or structural changes may be made without departing from the scopeof the present disclosure. As used herein, designators such as “n”,particularly with respect to reference numerals in the drawings,indicate that a number of the particular feature so designated can beincluded. As used herein, “a number of” a particular thing refers to oneor more of such things (e.g., a number of memory arrays can refer to oneor more memory arrays). A “plurality of” is intended to refer to morethan one of such things.

The figures herein follow a numbering convention in which the firstdigit or digits correspond to the drawing figure number and theremaining digits identify an element or component in the drawing.Similar elements or components between different figures may beidentified by the use of similar digits. For example, 150 may referenceelement “50” in FIG. 1, and a similar element may be referenced as 250in FIG. 2. As will be appreciated, elements shown in the variousembodiments herein can be added, exchanged, and/or eliminated so as toprovide a number of additional embodiments of the present disclosure. Inaddition, as will be appreciated, the proportion and the relative scaleof the elements provided in the figures are intended to illustratecertain embodiments of the present invention, and should not be taken ina limiting sense.

FIG. 1 is a block diagram of an apparatus in the form of a computingsystem 100 including a memory device 120 in accordance with a number ofembodiments of the present disclosure. As used herein, a memory device120, controller 140, channel controller 143, memory array 130, and/orsensing circuitry 150 might also be separately considered an“apparatus.”

System 100 includes a host 111 coupled (e.g., connected) to memorydevice 120, which includes a memory array 130. Host 111 can be a hostsystem such as a personal laptop computer, a desktop computer, a digitalcamera, a smart phone, or a memory card reader, among various othertypes of hosts. Host 111 can include a system motherboard and/orbackplane and can include a number of processing resources (e.g., one ormore processors, microprocessors, or some other type of controllingcircuitry). The system 100 can include separate integrated circuits orboth the host 111 and the memory device 120 can be part of a sameintegrated circuit (e.g., on a same chip). The system 100 can be, forinstance, a server system and/or a high performance computing (HPC)system and/or a portion thereof. Although the example shown in FIG. 1illustrates a system having a Von Neumann architecture, embodiments ofthe present disclosure can be implemented in non-Von Neumannarchitectures, which may not include one or more components (e.g., CPU,ALU, etc.) often associated with a Von Neumann architecture.

For clarity, the system 100 has been simplified to focus on featureswith particular relevance to the present disclosure. The memory array130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAMarray, RRAM array, NAND flash array, and/or NOR flash array, forinstance. The array 130 can comprise memory cells arranged in rowscoupled by access lines, which may be referred to herein as word linesor select lines, and columns coupled by sense lines, which may bereferred to herein as data lines or digit lines. Although a single array130 is shown in FIG. 1, embodiments are not so limited. For instance,memory device 120 may include a number of arrays 130 (e.g., a number ofbanks of DRAM cells, NAND flash cells, etc.).

The memory device 120 includes address circuitry 142 to latch addresssignals for data provided over a bus 156 (e.g., a data/address bus)through I/O circuitry 144. Status and/or exception information can beprovided from the controller 140 on the memory device 120 to a channelcontroller 143, through a high speed interface (HSI) including anout-of-band bus 157, which in turn can be provided from the channelcontroller 143 to the host 111. Address signals are received throughaddress circuitry 142 and decoded by a row decoder 146 and a columndecoder 152 to access the memory array 130. Data can be read from memoryarray 130 by sensing voltage and/or current changes on the digit linesusing sensing circuitry 150. The sensing circuitry 150 can read andlatch a page (e.g., row) of data from the memory array 130. The I/Ocircuitry 144 can be used for bi-directional data communication withhost 111 over the bus 156. The write circuitry 148 can be used to writedata to the memory array 130.

Controller 140 (e.g., memory controller) decodes signals provided bycontrol bus 154 from the host 111. These signals can include chip enablesignals, write enable signals, and address latch signals that are usedto control operations performed on the memory array 130, including dataread, data write, and data erase operations. In various embodiments, thecontroller 140 is responsible for executing instructions from the host111 and sequencing access to the array 130. The controller 140 can be astate machine, sequencer, or some other type of controller and includehardware and/or firmware (e.g., microcode instructions) in the form ofan application specific integrated circuit (ASIC). In some embodiments,the controller 140 may include cache 171. The controller 140 cancontrol, for example, sensing circuitry in accordance with embodimentsdescribed herein. For example, the controller 140 can control generationof clock signals and application of the clock signals to computecomponents in association with performing logical operations and/or datashifting operations.

As described further below, in a number of embodiments, the sensingcircuitry 150 can comprise a plurality of sensing components, which caneach include a sense amplifier and a compute component. The computecomponent may also be referred to herein as an accumulator, and can beused to perform logical operations (e.g., on data associated withcomplementary digit lines). According to various embodiments, thecompute component can comprise a number of storage locations (e.g.,latches) that can serve as stages of a shift register, for example. In anumber of embodiments, the sensing circuitry 150 can be used to performlogical operations using data stored in array 130 as inputs and/or storethe results of the logical operations back to the array 130 withouttransferring data via a digit line address access (e.g., without firinga column decode signal). For instance, various operations (e.g., computefunctions) can be performed using, and within, sensing circuitry 150rather than (or in association with) being performed by processingresources external to the sensing circuitry (e.g., by a processingresource associated with host 111 and/or other processing circuitry,such as ALU circuitry, located on device 120 (e.g., on controller 140 orelsewhere)).

In various previous approaches, data associated with an operand, forinstance, would be read from memory via sensing circuitry and providedto external ALU circuitry via I/O lines (e.g., via local I/O linesand/or global I/O lines). The external ALU circuitry could include anumber of registers and would perform compute functions using theoperands, and the result would be transferred back to the array via theI/O lines. In contrast, in a number of embodiments of the presentdisclosure, sensing circuitry 150 is configured to perform logicaloperations on data stored in memory array 130 and store the result backto the memory array 130 without enabling an I/O line (e.g., a local I/Oline) coupled to the sensing circuitry 150. The sensing circuitry 150can be formed on pitch with the memory cells of the array. An exampleconfiguration of the sensing circuitry 150 being formed on pitch isillustrated in FIG. 7. Additional logic circuitry 170 can be coupled tothe sensing circuitry 150 and can be used to store (e.g., cache and/orbuffer) results of operations described herein.

In a number of embodiments, circuitry external to array 130 and sensingcircuitry 150 is not needed to perform compute functions as the sensingcircuitry 150 can perform the appropriate logical operations to performsuch compute functions without the use of an external processingresource. Therefore, the sensing circuitry 150 may be used to complimentand/or to replace, at least to some extent, such an external processingresource (or at least the bandwidth consumption of such an externalprocessing resource).

However, in a number of embodiments, the sensing circuitry 150 may beused to perform logical operations (e.g., to execute instructions) inaddition to logical operations performed by an external processingresource (e.g., host 111). For instance, host 111 and/or sensingcircuitry 150 may be limited to performing only certain logicaloperations and/or a certain number of logical operations.

Enabling an I/O line can include enabling (e.g., turning on) atransistor having a gate coupled to a decode signal (e.g., a columndecode signal) and a source/drain coupled to the I/O line. However,embodiments are not limited to performing logical operations usingsensing circuitry (e.g., 150) without enabling column decode lines ofthe array. Whether or not local I/O lines are used in association withperforming logical operations via sensing circuitry 150, the local I/Oline(s) may be enabled in order to transfer a result to a suitablelocation other than back to the array 130 (e.g., to an externalregister).

FIG. 2 is a schematic diagram illustrating a portion of a memory array230 including sensing circuitry in accordance with a number ofembodiments of the present disclosure. FIG. 2 illustrates one sensingcomponent 250 which can be one of a number of sensing componentscorresponding to sensing circuitry 150 shown in FIG. 1. In the exampleshown in FIG. 2, the memory array 230 is a DRAM array of 1T1C (onetransistor one capacitor) memory cells in which a transistor serves asthe access device and a capacitor serves as the storage element;although other embodiments of configurations can be used (e.g., 2T2Cwith two transistors and two capacitors per memory cell). In thisexample, a first memory cell comprises transistor 202-1 and capacitor203-1, and a second memory cell comprises transistor 202-2 and capacitor203-2, etc.

The cells of the memory array 230 can be arranged in rows coupled byaccess lines 204-X (Row X), 204-Y (Row Y), etc., and columns coupled bypairs of complementary digit lines (e.g., digit lines 205-1 labelledDIGIT(n) and 205-2 labelled DIGIT(n)_ in FIG. 2). Although only one pairof complementary digit lines are shown in FIG. 2, embodiments of thepresent disclosure are not so limited, and an array of memory cells caninclude additional columns of memory cells and complementary digit lines(e.g., 4,096, 8,192, 16,384, etc.).

Memory cells can be coupled to different digit lines and word lines. Forinstance, in this example, a first source/drain region of transistor202-1 is coupled to digit line 205-1, a second source/drain region oftransistor 202-1 is coupled to capacitor 203-1, and a gate of transistor202-1 is coupled to word line 204-Y. A first source/drain region oftransistor 202-2 is coupled to digit line 205-2, a second source/drainregion of transistor 202-2 is coupled to capacitor 203-2, and a gate oftransistor 202-2 is coupled to word line 204-X. A cell plate, as shownin FIG. 2, can be coupled to each of capacitors 203-1 and 203-2. Thecell plate can be a common node to which a reference voltage (e.g.,ground) can be applied in various memory array configurations.

The digit lines 205-1 and 205-2 of memory array 230 are coupled tosensing component 250 in accordance with a number of embodiments of thepresent disclosure. In this example, the sensing component 250 comprisesa sense amplifier 206 and a compute component 231 corresponding to arespective column of memory cells (e.g., coupled to a respective pair ofcomplementary digit lines). The sense amplifier 206 is coupled to thepair of complementary digit lines 205-1 and 205-2. The sense amplifier206 is coupled to the compute component 231. In this example, thecompute component 231 includes selection logic circuitry 213 and computecomponent storage locations/shift logic circuitry 221, which are coupledvia accumulator signal lines 209-1 and 209-2. As used herein, “selectionlogic” can include logical operation selection logic, for example, logicselectively operated to perform selected logical operations (e.g.,Boolean logical operations). The selection logic circuitry 213 can becoupled to the pair of complementary digit lines 205-1 and 205-2 andconfigured to perform logical operations on data stored in array 230. Ina number of embodiments, compute component 231 can be formed on pitchwith the digit lines of the array. For example, the compute component231 may conform to a same pitch as adjacent digit lines of the array 230such that the compute component 231 and the sense amplifier 206 obey aparticular sense line pitch constraint (e.g., 4F, 6F, etc., where “F” isa feature size).

The sense amplifier 206 can be operated to determine a data value (e.g.,logic state) stored in a selected memory cell. The sense amplifier 206can comprise a cross coupled latch 215 (e.g., gates of a pair oftransistors, such as n-channel transistors 227-1 and 227-2 are crosscoupled with the gates of another pair of transistors, such as p-channeltransistors 229-1 and 229-2), which can be referred to herein as aprimary latch. However, embodiments are not limited to this example.

In operation, when a memory cell is being sensed (e.g., read), thevoltage on one of the digit lines 205-1 or 205-2 will be slightlygreater than the voltage on the other one of digit lines 205-1 or 205-2.An ACT signal and an RNL* signal can be activated (e.g., ACT is drivenhigh to a rail voltage such as VDD and RNL* is driven low to a railvoltage such as ground) to enable (e.g., fire) the sense amplifier 206.The digit line 205-1 or 205-2 having the lower voltage will turn on oneof the transistors 229-1 or 229-2 to a greater extent than the other oftransistors 229-1 or 229-2, thereby driving high the digit line 205-1 or205-2 having the higher voltage to a greater extent than the other digitline 205-1 or 205-2 is driven high.

Similarly, the digit line 205-1 or 205-2 having the higher voltage willturn on one of the transistors 227-1 or 227-2 to a greater extent thanthe other of the transistors 227-1 or 227-2, thereby driving low thedigit line 205-1 or 205-2 having the lower voltage to a greater extentthan the other digit line 205-1 or 205-2 is driven low. As a result,after a short delay, the digit line 205-1 or 205-2 having the slightlygreater voltage is driven to the voltage of the supply voltage VDDthrough a source transistor, and the other digit line 205-1 or 205-2 isdriven to the voltage of the reference voltage (e.g., ground) through asink transistor. Therefore, the cross coupled transistors 227-1 and227-2 and transistors 229-1 and 229-2 serve as a sense amplifier pair,which amplify the differential voltage on the digit lines 205-1 and205-2 and operate to store (e.g., latch) a data value sensed from theselected memory cell.

Embodiments are not limited to the sensing component configurationillustrated in FIG. 2. As an example, the sense amplifier 206 can be acurrent-mode sense amplifier and/or a single-ended sense amplifier(e.g., sense amplifier coupled to one digit line). Also, embodiments ofthe present disclosure are not limited to a folded digit linearchitecture such as that shown in FIG. 2.

In this example, the sense amplifier 206 includes equilibrationcircuitry 214, which can be configured to equilibrate the digit lines205-1 and 205-2. The equilibration circuitry 214 comprises a transistor224 coupled between digit lines 205-1 and 205-2. The equilibrationcircuitry 214 also comprises transistors 225-1 and 225-2 each having afirst source/drain region coupled to an equilibration voltage (e.g.,VDD/2), where VDD is a supply voltage associated with the array. Asecond source/drain region of transistor 225-1 is coupled to digit line205-1, and a second source/drain region of transistor 225-2 is coupledto digit line 205-2. Gates of transistors 224, 225-1, and 225-2 can becoupled together and to an equilibration (EQ) control signal line 226.As such, activating EQ enables the transistors 224, 225-1, and 225-2,which effectively shorts digit lines 205-1 and 205-2 together and to theequilibration voltage (e.g., VDD/2). Although FIG. 2 shows senseamplifier 206 comprising the equilibration circuitry 214, embodimentsare not so limited, and the equilibration circuitry 214 may beimplemented discretely from the sense amplifier 206, implemented in adifferent configuration than that shown in FIG. 2, or not implemented atall.

FIG. 3 is a schematic diagram illustrating a portion of a memory arrayincluding compute component 331 comprising selection logic circuitry 313and compute component storage location(s)/shift logic circuitry 321 inaccordance with a number of embodiments of the present disclosure.Although not shown, memory cells, such as those described in FIG. 2, arecoupled to pairs of complementary sense lines (e.g., digit lines 305-1and 305-2). The selection logic circuitry 313 illustrated in FIG. 3 isan example of logic circuitry that can be used to perform operations inaccordance with embodiments of the present disclosure. In this example,the selection logic circuitry 313 comprises four pairs of transistors373-1/373-2, 375-1/375-2, 377-1/377-2, and 379-1/379-2 coupled to thepair of complementary digit lines 305-1 and 305-2 via their source/drainregions. The gates of the transistor pairs 373-1/373-2, 375-1/375-2,377-1/377-2, and 379-1/379-2 are configured to receive respectiveselection logic signals BOOL0, BOOL1, BOOL2, and BOOL3. The selectionlogic signals can be selectively operated to perform logical operationsusing the sensing circuitry as described in more detail with respect toFIGS. 7A-7B.

In the example shown in FIG. 3, a first source/drain region oftransistor 373-1 is coupled to sense line 305-1 and a first source/drainregion of transistor 373-2 is coupled to sense line 305-2, a firstsource/drain region of transistor 375-1 is coupled to sense line 305-2and a first source/drain region of transistor 375-2 is coupled to senseline 305-1, a first source/drain region of transistor 377-1 is coupledto sense line 305-1 and a first source/drain region of transistor 377-2is coupled to sense line 305-2, and a first source/drain region oftransistor 379-1 is coupled to sense line 305-2 and a first source/drainregion of transistor 379-2 is coupled to sense line 305-1.

The selection logic circuitry 313 can be coupled to the computecomponent 331 and/or compute component storage location(s)/shift logicalcircuitry 321 via the first storage location lines 309-1 and 309-2and/or the second storage location lines 310-1 and 310-2. The computecomponent 331 can be analogous to the compute component 631 illustratedin FIG. 6 and discussed in more detail herein. The first storagelocation lines 309-1 and 309-2 can be coupled to source drain regions oftransistors other than the four pairs of transistors previouslydescribed. In some embodiments, the second storage location line 310-1can couple node 364 of the compute component 331 (shown in detail as thecompute component 631 in FIG. 6) to gates and source drain regions oftransistors (e.g., transistor 308-1) other than the four pairs oftransistors previously described. The second storage location line 310-2can couple node 366 of the compute component 331 (shown in detail as thecompute component 631 in FIG. 6) to gates and source drain regions oftransistors (e.g., transistor 308-2) other than the four pairs oftransistors previously described. In some embodiments, a source/drainregion of each of the transistors 308-1 and 308-2 can be coupled to areference voltage (e.g., Vss).

In some embodiments, the two n-channel transistors 308-1 and 308-2 maybe operated to cause nodes 364 and 366 to be grounded when a logicalmask value is low, thereby selectively disabling a logical operation fora respective sensing circuitry. In some embodiments, a p-channeltransistor 334 is provided to reduce contention between nodes 364 and366 as they are brought to ground, for example. In some embodiments, ann-channel transistor 336 may be provided to globally clear storedlogical operation values simultaneously.

If a first storage location (e.g., first storage location 633illustrated in FIG. 6) is the destination of the logical operation, theoriginal state of the first storage location may be held dynamically bycapacitance when the SHIFT 1 control signal line (e.g., SHIFT1 controlsignal line 681 illustrated in FIG. 6) and the SHIFT 2 control signalline (e.g., SHIFT1 control signal line 682 illustrated in FIG. 6) aredisabled. This may allow for a possible new state to be written fromselection logic circuitry 313, for example via first storage locationsignal lines 309-1 and 309-2.

In some embodiments, depending on the logical operation and the state ofthe sense amplifier operand, the first storage location signal lines309-1 and 309-2 may not be driven from the selection logic circuitry 313such that the original value of the first storage location 633 may bepreserved when the SHIFT 1 control signal line 681 and the SHIFT 2control signal line 682 are enabled as part of the logical operation.This may allow for a signal on nodes 364 and 366 to be held by dynamiccapacitance, for example.

In some embodiments, the selection logic circuitry 313 and/or thecompute component 331 can include logic circuitry storage location 332.Logic circuitry storage location 332 may be configured to actively store(e.g., latch) a data value received thereto. For example, logiccircuitry storage location 332 can comprise a latch that can beconfigured to receive a data value from the first storage location 633,and may actively store the data value. In some embodiments, logiccircuitry storage location 332 can store an indication of whether alogical operation is to be selectively performed between an operandstored in the sensing circuitry and an operand stored in the senseamplifier.

FIG. 4 is another schematic diagram illustrating a portion of a memoryarray including compute component 431 comprising selection logiccircuitry 413 and compute component storage location(s)/shift logiccircuitry 421 in accordance with a number of embodiments of the presentdisclosure. Although not shown, memory cells, such as those described inFIG. 2, are coupled to pairs of complementary sense lines (e.g., digitlines 405-1 and 405-2). The selection logic circuitry 413 illustrated inFIG. 4 is an example of logic circuitry that can be used to performoperations in accordance with embodiments of the present disclosure. Inthis example, the selection logic circuitry 413 comprises four pairs oftransistors 473-1/473-2, 475-1/475-2, 477-1/477-2, and 479-1/479-2coupled to the pair of complementary digit lines 405-1 and 405-2 viatheir source/drain regions. The gates of the transistor pairs473-1/473-2, 475-1/475-2, 477-1/477-2, and 479-1/479-2 are configured toreceive respective selection logic signals BOOL0, BOOL1, BOOL2, andBOOL3. The selection logic signals can be selectively operated toperform logical operations using the sensing circuitry as described inmore detail with respect to FIGS. 7A-7B.

In the example shown in FIG. 4, a first source/drain region oftransistor 473-1 is coupled to sense line 405-1 and a first source/drainregion of transistor 473-2 is coupled to sense line 405-2, a firstsource/drain region of transistor 475-1 is coupled to sense line 405-2and a first source/drain region of transistor 475-2 is coupled to senseline 405-1, a first source/drain region of transistor 477-1 is coupledto sense line 405-1 and a first source/drain region of transistor 477-2is coupled to sense line 405-2, and a first source/drain region oftransistor 479-1 is coupled to sense line 405-2 and a first source/drainregion of transistor 479-2 is coupled to sense line 405-1.

The selection logic circuitry 413 can be coupled to the computecomponent 431 via the first storage location lines 409-1 and 409-2and/or the second storage location lines 410-1 and 410-2. The computecomponent 431 can be analogous to the compute component 631 illustratedin FIG. 6 and discussed in more detail herein. In some embodiments, thefirst storage location lines 409-1 and 409-2 can be coupled to sourcedrain regions of transistors other than the four pairs of transistorspreviously described. The second storage location line 410-1 can couplenode 464 of the compute component 431 to gates and source drain regionsof transistors (e.g., 408-1) other than the four pairs of transistorspreviously described. The second storage location line 410-2 can couplenode 466 of the compute component 431 to gates and source drain regionsof transistors (e.g., transistor 408-2) other than the four pairs oftransistors previously described. A terminal of each of the transistors408-1 and 408-2 can be coupled to a reference voltage (e.g., Vss).

In some approaches, space limitations and/or layout difficulties mayarise due to insufficient routing paths between the selection logiccircuitry 413 and compute component 431. In some embodiments, theselimitations and/or difficulties may be alleviated by adding an activearea to the selection logic circuitry 413. For example, spacelimitations and/or layout difficulties associated with selectivelyperforming logical operations may be alleviated by providing theselection logic circuitry 413 with a mask storage location 441, asillustrated in FIG. 4.

In some embodiments, a p-channel transistor 434 is provided to reducecontention between nodes 464 and 466 as they are discharged to ground.In some embodiments, n-channel transistor 436 may be provided toglobally clear stored logical operation values simultaneously. Asillustrated in FIG. 4, the selection logic circuitry 413 may include alogic circuitry storage location 432, and a mask storage location 441.In some embodiments, the mask storage location 441 may be coupled to thep-channel transistor 434 at a source drain region of the p-channeltransistor 434.

In some embodiments, the configuration illustrated in FIG. 4 may allowfor data values to be masked (e.g., data values with which logicaloperations are to be selectively performed) to be transferred betweenthe logic selection circuitry 413 and the compute component 431 usingfirst storage location lines 409-1 and 409-2 and/or the pair ofcomplimentary digit lines 405-1 and 405-2. By using first storagelocation lines 409-1 and 409-2 and/or the pair of complimentary digitlines 405-1 and 405-2 to transfer data values to be masked between thelogic selection circuitry 413 and the compute component 431, operationsmay be performed in less time compared to some approaches.

FIG. 5 is yet another schematic diagram illustrating a portion of amemory array including compute component 531 comprising selection logiccircuitry 513 and compute component storage location(s)/shift logiccircuitry 521 in accordance with a number of embodiments of the presentdisclosure. Although not shown, memory cells, such as those described inFIG. 2, are coupled to pairs of complementary sense lines (e.g., digitlines 505-1 and 505-2). The selection logic circuitry 513 illustrated inFIG. 5 is an example of logic circuitry that can be used to performoperations in accordance with embodiments of the present disclosure. Inthis example, the selection logic circuitry 513 comprises four pairs oftransistors 573-1/573-2, 575-1/575-2, 577-1/577-2, and 579-1/579-2coupled to the pair of complementary digit lines 505-1 and 505-2 viatheir source/drain regions. The gates of the transistor pairs573-1/573-2, 575-1/575-2, 577-1/577-2, and 579-1/579-2 are configured toreceive respective selection logic signals BOOL0, BOOL1, BOOL2, andBOOL3. The selection logic signals can be selectively operated toperform logical operations using the sensing circuitry as described inmore detail with respect to FIGS. 7A-7B.

In the example shown in FIG. 5, a first source/drain region oftransistor 573-1 is coupled to sense line 505-1 and a first source/drainregion of transistor 573-2 is coupled to sense line 505-2, a firstsource/drain region of transistor 575-1 is coupled to sense line 505-2and a first source/drain region of transistor 575-2 is coupled to senseline 505-1, a first source/drain region of transistor 577-1 is coupledto sense line 505-1 and a first source/drain region of transistor 577-2is coupled to sense line 505-2, and a first source/drain region oftransistor 579-1 is coupled to sense line 505-2 and a first source/drainregion of transistor 579-2 is coupled to sense line 505-1.

The selection logic circuitry 513 can be coupled to the computecomponent 531 via the first storage location lines 509-1 and 509-2 andthe second storage location lines 510-1 and 510-2. The compute component531 can be analogous to the compute component 631 illustrated in FIG. 6and discussed in more detail herein. The first storage location lines509-1 and 509-2 can be coupled to source drain regions of transistorsother than the four pairs of transistors previously described. Thesecond storage location line 510-1 can couple node 564 of the computecomponent 531 to gates and source drain regions of transistors (e.g.,508-1) other than the four pairs of transistors previously described.The second storage location line 510-2 can couple node 566 of thecompute component 531 to gates and source drain regions of transistors(e.g., transistor 508-2) other than the four pairs of transistorspreviously described. A terminal of each of the transistors 508-1 and508-2 can be coupled to a reference voltage (e.g., Vss).

In some embodiments, the selection logic circuitry 513 and/or thecompute component 531 can include logic circuitry storage location 532.Logic circuitry storage location 532 may be configured to actively store(e.g., latch) a data value received thereto. For example, logiccircuitry storage location 532 can comprise a latch that can beconfigured to receive a data value from the first storage location 633,and may actively store the data value. In some embodiments, logiccircuitry storage location 532 can store an indication of whether alogical operation is to be selectively performed between an operandstored in the sensing circuitry and an operand stored in the senseamplifier.

As illustrated in FIG. 5, a column repair (ColRep) signal line can beconnected to node 564 and/or node 566. In some embodiments, a signal maybe provided on ColRep signal line to provide a column repair signal thatmay be used to provide a repair capability by blocking signals carriedon the first storage location lines 509-1 and 509-2 and/or the secondstorage location lines 510-1 and 510-2. For example, a signal may beprovided on ColRep signal line to block signals carried on the firststorage location lines 509-1 and 509-2 and/or the second storagelocation lines 510-1 and 510-2 to remove (e.g., short) sense amplifier506 and/or compute component 531 such that sense amplifier 506 and/orcompute component 531 are effectively removed from a particular sensingcomponent.

In some embodiments, ColRep signal line is connected to physicallyadjacent storage locations (e.g., storage locations 633 and 635illustrated in FIG. 6) that are connected to a same main input/output(MIO) signal line (not shown). The MIO signal line may be connected tothe physically adjacent storage locations via a multiplexer that may beconfigured to multiplex column select signals to the MIO. In someembodiments, signals may be provided to the ColRep signal line duringshifting operations, but may not be utilized while logical operationsare performed.

In some embodiments, the lack of signals on the ColRep signal lineduring performance of logical operations allows for the ColRep signalline to be used when a column repair signal is not active on ColRepsignal line to facilitate selective performance of logical operations.For example, an indication of whether a logical operation is to beselectively performed may be sent via ColRep signal line when shiftingsignals are not present on ColRep signal line. In some embodiments, theindication can be an indication that a logical operation is not to beperformed between an operand stored in the sensing circuitry (e.g., anoperand stored in a storage location associated with the computecomponent 531) and an operand stored in the sense amplifier 506.

In some embodiments, ColRep signal may be multiplexed to a plurality ofcompute components 531 such that a signal on ColRep signal line is sentto a plurality of storage locations associated with a plurality ofcompute components 531. For example, ColRep signal may be multiplexed toeight compute components 531. In some embodiments, ColRep signal canprovide the indication of whether a logical operation is to beselectively performed to a portion of a row of memory array (e.g., about2K bits per ColRep signal).

FIG. 6 is a schematic diagram illustrating sensing circuitry inaccordance with a number of embodiments of the present disclosure. FIG.6 shows a number of sense amplifiers 606 coupled to respective pairs ofcomplementary sense lines 605-1 and 605-2, and a corresponding number ofcompute components 631 coupled to the sense amplifiers 606. The senseamplifiers 606 and compute components 631 shown in FIG. 6 can correspondto sensing circuitry 150 shown in FIG. 1, for example. The sensingcircuitry shown in FIG. 6 includes selection logic circuitry 613, whichcan be operated as described further herein. The selection logiccircuitry 613 shown in FIG. 6 can correspond to selection logiccircuitry 213 shown in FIG. 2 or selection logic circuitry 313/413/513shown in FIGS. 3, 4, and 5, for example.

Although not shown, memory cells, such as those described in FIG. 2, arecoupled to the pairs of complementary sense lines 605-1 and 605-2 Thecells of the memory array can be arranged in rows coupled by word linesand columns coupled by pairs of complementary sense linesDIGIT(n−1)/DIGIT(n−1)_, DIGIT(n)/DIGIT(n)_, DIGIT(n+1)/DIGIT(n+1)_, etc.The individual sense lines corresponding to each pair of complementarysense lines can also be referred to as data lines. Although only threepairs of complementary sense lines (e.g., three columns) are shown inFIG. 6, embodiments of the present disclosure are not so limited.

As shown in FIG. 6, the sensing components can comprise a senseamplifier 606 and a compute component 631, which comprises selectionlogic circuitry 613 and compute component storage locations/shift logiccircuitry 621 corresponding to respective columns of memory cells (e.g.,coupled to respective pairs of complementary sense lines). The computecomponent 631 may include storage location 632. Although storagelocation 632 is illustrated as part of the selection logic circuitry613, embodiments are not so limited, and storage location 632 can belocated at other locations within the compute component 631. Storagelocation 632 may be a cross-coupled latch, D latch, or other circuitconfiguration capable of storing an operand (e.g., a data value). Thesense amplifier 606 can comprise, for example, a cross coupled latch,which can be referred to herein as a primary latch. The sense amplifiers606 can be configured, for example, as described with respect to FIG. 2.

A data value present on the pair of complementary sense lines 605-1 and605-2 can be loaded into the corresponding compute component 631. Insome embodiments, the compute component storage locations/shift logiccircuitry 621 can include a pair of compute component storage locations(e.g., first compute component storage location 633 and second computecomponent storage location 635) associated with each compute component631. In some embodiments, the first compute component storage location633 and the second compute component storage location 635 can comprisestages of a shift register. For example, in at least one embodiment, thecompute component storage locations (e.g., first compute componentstorage location 633 and second compute component storage location 635)can serve as respective stages of a shift register capable of shiftingdata values (e.g., right and/or left) and/or performing rotationoperations (e.g., rotate right and/or rotate left). As an example, thedata values can be loaded into the compute component storage locationsof a corresponding compute component 631 by overwriting of the datavalues currently stored in the compute component storage locations ofthe corresponding compute components 631 with a data value stored in thecorresponding sense amplifier 606. The data value on the pair ofcomplementary sense lines 605-1 and 605-2 can be the data value storedin the sense amplifier 606 when the sense amplifier is enabled (e.g.,fired).

In some embodiments, a first latching/activation signal ACT is appliedto the two p-channel transistors 651-1 and 651-2 of the first computecomponent storage location 633 and a second latching/activation signalRNL* is applied to the two n-channel transistors 653-1 and 653-2 of thesecond compute component storage location 635. Similarly, a second ACTsignal is applied to the two p-channel transistors 655-1 and 655-2 ofthe second compute component storage location 635 and a second RNL*signal is applied to the two n-channel transistors 657-1 and 657-2 ofthe second compute component storage location 635. In some embodiments,the respective ACT and RNL* signals control operation of the firstcompute component storage location 633 and the second compute componentstorage location 635. As shown in FIG. 6, power to the first computecomponent storage location 633 and the second compute component storagelocation 635 can be provided via a pairs of complementary enable signals(e.g., EnA/EnC, and EnB/EnD, respectively). For example, first computecomponent storage location 633 is coupled to EnA at power node 691, andsecond compute component storage location is coupled to EnB at powernode 693. First compute component storage location 633 is coupled to EnCat power node 695, and second compute component storage location 635 iscoupled to EnD at power node 697. Although not shown in FIG. 6, a powersupply transistor can be coupled to each of the enable signals EnA, EnB,EnC, and EnD and to a reference voltage (e.g., Vss).

As shown in FIG. 6, signal input lines 637 and 639 are coupled torespective accumulator signal lines 609-1 and 609-2 at ST2 and SF1,respectively. In some embodiments, signal input lines 637 and 639 arecoupled to respective storage location lines 610-1 and 610-2 at SF2 andST1, respectively. In operation, the voltage on one of the signal inputlines 637 or 639 will be slightly greater than the voltage on one of theother signal input lines 637 or 639. The signal input line 637 or 639having the lower voltage will turn on one of the p-channel transistors651-1 or 651-2 in the first secondary latch (e.g., first computecomponent storage location 633) to a greater extent than the other ofp-channel transistors 651-1 or 651-2, thereby driving higher the firstcompute component storage location signal lines 609-1 or 609-2 having ahigher voltage to a greater extent than the other first computecomponent storage location signal line 609-1 or 609-2 is driven high.Similarly, the signal input line 637 or 639 having the lower voltagewill turn on one of the p-channel transistors 655-1 or 655-2 in thesecond secondary latch (e.g., second compute component storage location635) to a greater extent than the other of transistors 655-1 or 655-2,thereby driving higher the first compute component storage locationsignal line 609-1 or 609-2 having a higher voltage to a greater extentthan the other first compute component storage location signal line609-1 or 609-2 is driven high.

The signal input line 637 or 639 having the higher voltage will turn onone of the n-channel transistors 653-1 or 653-2 in the first secondarylatch to a greater extent than the other of the transistors 653-1 or653-2, thereby driving lower the first s compute component storagelocation signal line 609-1 or 609-2 having the lower voltage to agreater extent than the other first compute component storage locationsignal line 609-1 or 609-2 is driven low. Similarly, the signal inputline 637 or 639 having the higher voltage will turn on one of then-channel transistors 657-1 or 657-2 in the second secondary latch to agreater extent than the other of the transistors 657-1 or 657-2, therebydriving lower the first compute component storage location signal line609-1 or 609-2 having the lower voltage to a greater extent than theother first compute component storage location signal line 609-1 or609-2 is driven low. Accordingly, as used herein, a “high side” or “highnode,” and a “low side” or “low node” of the first compute componentstorage location 633 and/or the second compute component storagelocation 635 refer to a side of the storage location on which adifferential voltage is comparatively high or comparatively low,respectively.

The first and second sampling transistors 683-1 and 683-2 can becontrolled by a shift signal. For example, an input of first computecomponent storage location 633 can be coupled to the first and secondsampling transistors 683-1 and 683-2, and an input of second computecomponent storage location 635 can be coupled to the third and fourthsampling transistors 685-1 and 685-2. In some embodiments, the first andsecond sampling transistors 683-1 and 683-2 and/or the third and fourthsampling transistors 685-1 and 685-2 can control storing and/or shiftingof data values between the first compute component storage location 633and the second compute component storage location 635.

In some embodiments, the first and second sampling transistors 683-1 and683-2 and/or the third and fourth sampling transistors 685-1 and 685-2may be enabled or disabled in response to a control signal. For example,the first and second sampling transistors 683-1 and 683-2 may be enabledor disabled in response to a SHIFT 1 control signal line 681, and thethird and fourth sampling transistors 685-1 and 685-2 may be enabled ordisabled in response to a SHIFT 2 control signal line 682, as describedin more detail, herein. The SHIFT 1 control signal line 681 can carry ashift right phase 2, left phase 1 control signal, and the SHIFT 2control signal line 682 can carry a shift right phase 1, left phase 2control signal.

In some embodiments, transferring a data value from the first computecomponent storage location 633 to the second compute component storagelocation 635 is carried out by controlling which of power nodes 691,693, 695, and 697 are providing a voltage to each of the first computecomponent storage location 633 and the second compute component storagelocation 635 over time. For example, transferring a data value from thefirst compute component storage location 633 to the second computecomponent storage location 635 can include applying a voltage to firstcompute component storage location at power nodes 691 and/or 695 when avoltage is not applied to second storage location 635 at power nodes 693and/or 697, and synchronously switching the applied voltages such thatthe voltage is no longer applied to first compute component storagelocation 633 at power nodes 691 and/or 695 and the voltage is insteadapplied to second compute component storage location 635 at power nodes693 and/or 697. In some embodiments, the first and second samplingtransistors 683-1 and 683-2 and/or the third and fourth samplingtransistors 685-1 and 685-2 may be enabled when the voltage is switchedfrom power node 691 and/or 695 to power node 693 and/or 697, or viceversa. In some embodiments, the first compute component storage location633 and/or the second compute component storage location 635 areequalized when their respective power node 691/695 or 693/697 is notreceiving a voltage signal.

If a first compute component storage location 633 is the destination ofa logical operation, the original state of the first compute componentstorage location may be held dynamically by capacitance when the SHIFT 1control signal line 681 and the SHIFT 2 control signal line 682 aredisabled. This may allow for a possible new data value to be writtenfrom selection logic circuitry 613, for example via first computecomponent storage location signal lines 609-1 and 609-2.

The first compute component storage location 633 and the second computecomponent storage location 635 can each operate in several stages. Afirst stage of operation can include an equalization stage inpreparation for receiving a differential input signal. In someembodiments, the differential input signal can be received from signalinput lines 637 and/or 639. A second stage of operation can include asample stage in which the differential input signal is received by thefirst compute component storage location 633 and/or the second computecomponent storage location 635. For example, a data value can bereceived and/or stored by the first compute component storage location633 and/or the second compute component storage location 635 based onthe differential input signal on compute component signal lines 609-1and 609-2. A third stage of operation can include an “amplify and latch”stage where the received differential input signal is amplified andlatched by the first compute component storage location 633 and/or thesecond compute component storage location 635.

In some embodiments, the third stage can be facilitated by cross coupledtransistors 653-1 and 653-2, and 651-1 and 651-2 associated with thefirst compute component storage location 633, which can amplify thedifferential voltage on signal input lines 637 and 639 and operate tolatch a data value received at the first compute component storagelocation 633. Similarly, coupled transistors 657-1 and 657-2, and 655-1and 655-2 associated with the second compute component storage location635, can amplify the differential voltage on signal input lines 637 and639 and operate to latch a data value received at the second computecomponent storage location 635. In some embodiments, the third stage caninclude driving the data value from one compute component storagelocation to a next compute component storage location (e.g., driving thedata value from the first compute component storage location 633 to thesecond compute component storage location 635).

Although not shown in FIG. 6, each column of memory cells can be coupledto a column decode line that can be activated to transfer, via a localI/O line, data values from corresponding sense amplifiers 606 and/orcompute components 631 to a control component external to the array suchas an external processing resource (e.g., host processor and/or otherfunctional unit circuitry). The column decode line can be coupled to acolumn decoder. However, as described herein, in a number ofembodiments, data need not be transferred via such I/O lines to performshift operations in accordance with embodiments of the presentdisclosure. In a number of embodiments, sense amplifiers 606 and computecomponents 631 may be operated to perform logical operations withouttransferring data to a control component external to the array, forinstance. As used herein, transferring data, which may also be referredto as moving data or shifting data is an inclusive term that caninclude, for example, copying data from a source location to adestination location and/or moving data from a source location to adestination location without necessarily maintaining a copy of the dataat the source location.

Embodiments of the present disclosure are not limited to the logicaloperation performance capability described in association with thecompute components 631. For example, a number of embodiments can includecircuitry in addition to and/or instead of the circuitry described inassociation with the compute component 631.

FIG. 7A is a logic table illustrating selectable logical operationresults implemented by sensing circuitry in accordance with a number ofembodiments of the present disclosure. FIG. 7A shows a resultant datavalue that is initially stored in the first compute component storagelocation (e.g., first compute component storage location 633 shown inFIG. 6) after the sense amplifier (e.g., sense amplifier 606 shown inFIG. 6 is enabled (e.g., fired). Starting data values (e.g., operands)for a particular logical operation can be stored in the sense amplifierand/or the first compute component storage location from the memoryarray. For the purpose of describing FIGS. 7A and 7B, a first operand(e.g., “A”) is a data value that can be read from a memory array andstored in the first compute component storage location and a secondoperand (e.g., “B”), is a data value that can be read from the memoryarray by the sense amplifier. As described further below in associationwith FIG. 9, a number of embodiments can include reading operand A intoa sense amplifier (e.g., 606), transferring operand A from the senseamplifier to a first compute component storage location (e.g., 633),transferring operand A from the first compute component storage locationto a second compute component storage location (e.g., 632), and thenoperating the sensing circuitry to perform a selected logical operationbetween operand A and an operand B by activating the appropriatecorresponding selection logic signals (e.g., BOOL0, BOOL1, BOOL2, andBOOL3) at the appropriate time (e.g., either before or after enablingthe sense amplifier to sense operand B from a selected memory cell).

A selected logical operation between the first data value and a seconddata value can be performed based on the appropriate control signalscorresponding to the selected logical operation being provided to thelogic circuitry (e.g., selection logic circuitry 213 shown in FIG. 2,selections logic circuitry 313 shown in FIG. 3, selection logiccircuitry 413 shown in FIG. 4, etc.). For instance, in FIG. 7A, “RESULTIN FIRST STORAGE LOCATION—(AFTER SENSE AMP FIRE)” indicates that thecontrol signals corresponding to the selected logical operation areenabled after the sense amplifier is enabled, such that the result ofthe selected logical operation is initially stored in the first computecomponent storage location. Similarly, in FIG. 7B, “RESULT IN SENSEAMP—(BEFORE SENSE AMP FIRE)” indicates that the control signalscorresponding to the selected logical operation are enabled before thesense amplifier is enabled, such that the result of the selected logicaloperation is initially stored in the sense amplifier.

The logic table illustrated in FIG. 7A shows the starting data valuestored in the first compute component storage location in column A at770, and shows the starting data value stored in the sense amplifier incolumn B at 772. The various combinations of the control signals BOOL0,BOOL1, BOOL2, and BOOL3 are shown in FIG. 7A in the column headings inrow 774. For example, the column heading of “0110” indicates that theresults in that column correspond to control signal BOOL3 being a “0,”control signal BOOL2 being a “1,” control signal BOOL1 being a “1,” andcontrol signal BOOL0 being a “0.”

The results for each combination of starting data values in the firstcompute component storage location (“A”) and in the sense amplifier(“B”) can be summarized by the logical operation shown for each columnin row 776. For example, the result for the values of BOOL3, BOOL2,BOOL1, and BOOL0 of “0000” are summarized as “A” since the result(initially stored in the first storage location after the senseamplifier fires) is the same as the starting value in the first computecomponent storage location. Other columns of results are similarlyannotated in row 776, where “A*B” intends A AND B, “A+B” intends A OR B,and “AXB” intends A XOR B. By convention, a bar over a data value or alogical operation indicates an inverted value of the quantity shownunder the bar. For example, AXB bar intends NOT A XOR B, which is also AXNOR B.

FIG. 7B is another logic table illustrating selectable logical operationresults implemented by sensing circuitry in accordance with a number ofembodiments of the present disclosure. FIG. 7B shows a resultant datavalue that is initially stored in the sense amplifier (e.g., senseamplifier 606 shown in FIG. 6) after the sense amplifier is enabledcorresponding to the various combinations of control signals BOOL3,BOOL2, BOOL1, and BOOL0. The logic table illustrated is arranged similarto that described with respect to FIG. 7A, with the starting data valuestored in the first compute component storage location shown in column Aat 770, and the starting data value stored in the sense amplifier shownin column B at 772. The various combinations of the control signalsBOOL0, BOOL1, BOOL2, and BOOL3 is shown in FIG. 7B in the columnheadings shown in row 774, and the logical operation represented by eachrespective column of results shown in the column subheading at row 776.

In contrast with the logical operations summarized in the logic tableillustrated in FIG. 7A, which reflects a logical operation resultinitially stored in the first compute component storage location afterthe sense amplifier is enabled, the logical operations summarized in thelogic table illustrated in FIG. 7B reflects a logical operation resultinitially stored in the sense amplifier 606 after the sense amplifier isenabled (e.g., with the control signals corresponding to the selectedlogical operation being provided to the selection logic circuitry 213,313, 413, 513, 613 before the sense amplifier is enabled). The logicaloperations summarized in the logic table illustrated in FIG. 7B includeseveral different logical operations from those shown in the logic tableillustrated in FIG. 7A including “B” (the logical operation resultinitially stored in the sense amplifier after the sense amplifier isenabled is the same as the starting data value in the sense amplifier),“RESET” (the logical operation result initially stored in the senseamplifier after the sense amplifier is enabled is always set to “0”),and “SET” (the logical operation result initially stored in the senseamplifier after the sense amplifier is enabled is always set to “1”).

FIG. 8 is a table illustrating selective performance of a logicaloperation in accordance with a number of embodiments of the presentdisclosure. In the example of FIG. 8, A 873 represents data stored in astorage location (e.g., storage location 633 illustrated in FIG. 6)associated with the compute component (e.g., compute component 631illustrated in FIG. 6), Vm 875 represents a row of a memory array thatcontains an indication of whether a logical operation is to beselectively performed, Rn 877 represents data stored in a row of amemory array following a logical operation, and Rn AFTER MASK 879represents data stored in a row of a memory array following aselectively performed logical operation.

In some embodiments, data stored in Vm 875 can be transferred to one ormore storage locations represented by A 873. Subsequently, the data nowstored in the one or more storage locations represented by A 873 can betransferred to a different storage location (e.g., logic circuitrystorage location 332 illustrated in FIG. 3). Once the data aretransferred to the different storage location, a row of data from thememory array (e.g., ROW X illustrated in FIG. 2) can be transferred tothe one or more storage locations represented by A 873. Data stored inRn 877 can then be transferred to one or more sense amplifiers (e.g.,sense amplifier 206 illustrated in FIG. 2) associated with the sensingcircuitry, and data from A 873 can be selectively transferred to one ormore sense amplifiers based on the data stored in Vm 875. In someembodiments, a result of a logical operation associated with theforegoing steps may then be stored in Rn877 concurrently withselectively transferring the data from A 873 to the one or more senseamplifiers.

FIG. 9 is a timing diagram for performing a logical operation inaccordance with a number of embodiments of the present disclosure. Theexample described in FIG. 9 includes a logical AND operation performedbetween an operand A and an operand B using the sensing circuitrydescribed in FIGS. 3-6. Although embodiments are not so limited, forthis example, we assume operand A is initially stored in a memory cellcoupled to a particular row and column of an array, and operand B isinitially stored in a memory cell coupled to a different particular rowand to the same column.

At an initial time to, a data value (Previous Data) may be stored in(e.g., latched by) a first compute component storage location (e.g.,633). Data values may also be stored in the sense amplifier (e.g., 606)and/or one or more other compute component storage locations (e.g., 635,632). At time t₁, operand A is sensed (e.g., by activating the row towhich the cell storing operand A is coupled and enabling the senseamplifier 606) such that the sense amplifier stores the data value(e.g., Data A, which can be a logic 1 or 0) corresponding to operand A.At time t₂, the first compute component storage location (e.g., latch633) is disabled (e.g., EnA goes low and EnC goes high). While the latch633 is disabled, at time t₃ the logic selection signals BOOL0 and BOOL2are activated (with BOOL1 and BOOL3 remaining deactivated), which passesthe voltages on the digit lines DIGIT(n)/DIGIT(n)_ (e.g., the data valuecorresponding to operand A and stored in sense amplifier 606) throughone of transistor pairs (e.g., transistor pairs 373-1/373-2 and377-1/377-2), depending on which of complementary nodes 361-1 and 361-2is high (e.g., if node 361-1 is high and 361-2 is low, then transistorpair 367-1/367-2 will be enabled, and if node 361-1 is low and 361-2 ishigh, then transistor pair 369-1/369-2 will be enabled). At time t₄, thelatch 633 is enabled (e.g., EnA goes high and EnC goes low) to storeoperand A in latch 633.

The data value stored in the latch 633 can subsequently be transferredfrom latch 633 to compute component storage location 632. For example,at time t₅, the power nodes of compute component storage location 632are disabled (e.g., OpAct 361-1 goes low and OpActF 361-2 goes high) andat time t₆ Pass Acm goes high, which enables pass gates 308-1 and 308-2such that the voltage on line 309-1 is transferred to node 363-1 and thevoltage on line 309-2 is transferred to node 363-2. At time t₇ the latch632 is enabled (e.g., OpAct 361-1 goes high and OpActF 361-2 goes low)to store the operand A data value (e.g., DATA A) in latch 432, and attime t₈, Pass Acm returns low, which isolates the input nodes of latch632 from the input nodes of latch 633.

Between time t₈ and t₉, the row to which the cell storing operand B iscoupled is activated and the sense amplifier 606 is enabled. At time t₉,latch 633 is disabled (e.g., EnA goes low and EnC goes high). While thelatch 633 is disabled, at time t₁₀, the logic selection signal BOOL0 isactivated (with BOOL1, BOOL2, and BOOL3 remaining deactivated), since inthis example the operation (e.g., Op1) to be performed is a logical ANDoperation (see the table in FIG. 7A). BOOL0 going high enablestransistor pair 373-1/373-2, which couples the digit linesDIGIT(n)/DIGIT(n)_ to respective signal lines 309-1/309-2, depending onthe state of complementary nodes 363-1/363-2. For example, if node 363-1is high (and 363-2 is low), then transistor pair 367-1/367-2 will beenabled such that DIGIT(n)/DIGIT(n)_ are coupled to respective signallines 309-1/309-2, and if node 363-1 is low (and 363-2 is high), thentransistor pair 367-1/367-2 will be disabled such thatDIGIT(n)/DIGIT(n)_ remain decoupled (e.g., isolated) from respectivesignal lines 309-1/309-2.

At time t₁₁, the latch 633 is enabled (e.g., EnA goes high and EnC goeslow) such that the data value corresponding to the complementaryvoltages on signal lines 309-1/309-2 is stored in latch 633 as theresult of the logical operation (e.g., Operand A AND Operand B).

At time t₁₂, the power nodes of compute component storage location 632are disabled (e.g., OpAct 361-1 goes low and OpActF 361-2 goes high) andat time t₁₃ Pass Acm goes high, which enables pass gates 308-1 and 308-2such that the voltage on line 309-1 is transferred to node 363-1 and thevoltage on line 309-2 is transferred to node 363-2. At time t₁₄ thelatch 632 is enabled (e.g., OpAct 361-1 goes high and OpActF 361-2 goeslow) to store the operand A data value (e.g., DATA A) in latch 632, andat time t₁₅, Pass Acm returns low, which isolates the input nodes oflatch 632 from the input nodes of latch 633. In some embodiments,subsequent operations may be performed by repeating one or more of thesteps described above in connection with FIG. 9.

FIG. 10 illustrates an example configuration of sensing circuitry inaccordance with a number of embodiments of the present disclosure. Asillustrated in FIG. 10, the sensing circuitry can include a plurality ofsense amplifiers 1006-1, . . . , 1006-N, and compute component 1031.Each respective sense amplifier (e.g., sense amplifier 1006-1) may becoupled to the sensing circuitry 1031 by a pair of complementary senselines 1005-1/1005-2. As illustrated in FIG. 10, a respective senseamplifier (e.g., 1006-1) and a respective compute component 1031associated with the respective sense amplifier (e.g., 1006-1) can beformed such that each respective sense amplifier (e.g., 1006-1) and eachrespective compute component 1031 is located between a respective pairof complementary sense lines 1005-1/1005-2. For example, the respectivesense amplifiers 1006-1, . . . , 1006-N and compute components 1031 canbe formed on pitch with respective pairs of complementary sense lines(e.g., complementary sense lines 1005-1 and 1005-2) of an array ofmemory cells.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that anarrangement calculated to achieve the same results can be substitutedfor the specific embodiments shown. This disclosure is intended to coveradaptations or variations of one or more embodiments of the presentdisclosure. It is to be understood that the above description has beenmade in an illustrative fashion, and not a restrictive one. Combinationof the above embodiments, and other embodiments not specificallydescribed herein will be apparent to those of skill in the art uponreviewing the above description. The scope of the one or moreembodiments of the present disclosure includes other applications inwhich the above structures and methods are used. Therefore, the scope ofone or more embodiments of the present disclosure should be determinedwith reference to the appended claims, along with the full range ofequivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are groupedtogether in a single embodiment for the purpose of streamlining thedisclosure. This method of disclosure is not to be interpreted asreflecting an intention that the disclosed embodiments of the presentdisclosure have to use more features than are expressly recited in eachclaim. Rather, as the following claims reflect, inventive subject matterlies in less than all features of a single disclosed embodiment. Thus,the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment.

What is claimed is:
 1. An apparatus, comprising: a memory array; a senseamplifier coupled to the memory array; Boolean selection circuitrycoupled to the sense amplifier; an accumulator coupled to the Booleanselection circuitry; a latch coupled to the accumulator and the Booleanselection circuitry; and a controller configured to control the Booleanselection circuitry, the accumulator and the latch, wherein thecontroller is configured to cause a Boolean mask value to be storedusing the latch, and wherein the Boolean selection circuitry isconfigured to be selectively disabled responsive to the Boolean maskvalue.
 2. The apparatus of claim 1, wherein the accumulator furthercomprises a transistor configured to reduce an amount of contentionbetween nodes of the accumulator responsive to the Boolean selectioncircuitry being selectively disabled.
 3. The apparatus of claim 2,wherein the transistor is configured to reduce the amount of contentionbetween the nodes of the accumulator responsive to the nodes of theaccumulator being discharged to a ground reference potential.
 4. Theapparatus of claim 2, wherein the transistor is a p-channel transistor.5. The apparatus of claim 1, further comprising a transistor coupled tothe Boolean selection circuitry and configured to be enabled to clearthe Boolean mask value stored in the latch.
 6. The apparatus of claim 5,wherein the transistor is an n-channel transistor.
 7. The apparatus ofclaim 1, further comprising a column repair signal line coupled to nodesof the accumulator and configured to provide a repair capability to theapparatus.
 8. The apparatus of claim 7, wherein the column repair signalline is configured to block signals from the sense amplifier as part ofthe repair capability.
 9. The apparatus of claim 7, wherein the columnrepair signal line is configured to block signals from the accumulatoras part of the repair capability.
 10. An apparatus, comprising: a memoryarray; a sense amplifier coupled to the memory array; Boolean selectioncircuitry coupled to the sense amplifier; an accumulator coupled to theBoolean selection circuitry; a latch coupled to the accumulator; and aBoolean mask latch coupled to the Boolean selection circuitry andconfigured to store a Boolean mask value, wherein the Boolean selectioncircuitry is configured to be selectively disabled responsive to themask value.
 11. The apparatus of claim 10, wherein the sense amplifieris configured to store the Boolean mask value.
 12. The apparatus ofclaim 10, wherein the accumulator is configured to store the Booleanmask value.
 13. The apparatus of claim 10, further comprising: ap-channel transistor coupled to the Boolean selection circuitry andconfigured to reduce an amount of contention between nodes of theaccumulator responsive to the Boolean selection circuitry beingselectively disabled; and an n-channel transistor coupled to the Booleanselection circuitry and configured to clear the Boolean mask valuestored in the latch.
 14. The apparatus of claim 10, further comprising acolumn repair signal line coupled to nodes of the accumulator andconfigured to provide a repair capability to the apparatus by blockingsignals from the sense amplifier or the accumulator.
 15. A method,comprising: storing, using a latch coupled to an accumulator and Booleanselection circuitry associated with a memory array, a Boolean maskvalue; selectively disabling the Boolean selection circuitry responsiveto detection of the Boolean mask value; and preventing performance of alogical operation between an operand stored in the accumulator and anoperand stored in a sense amplifier coupled to the memory array byselectively disabling the Boolean selection circuitry.
 16. The method ofclaim 15, further comprising storing the Boolean mask value in theaccumulator or in a sense amplifier coupled to the Boolean selectioncircuitry.
 17. The method of claim 15, further comprising: dischargingnodes of the accumulator to a ground reference potential; and reducingan amount of contention between nodes of the accumulator by enabling atransistor coupled to the Boolean selection circuitry and theaccumulator.
 18. The method of claim 15, further comprising enabling atransistor coupled to the Boolean selection circuitry to clear theBoolean mask value stored in the latch.
 19. The method of claim 15,further comprising enabling a column repair signal line coupled to nodesof the accumulator to provide a repair capability to the accumulator,Boolean selection circuitry, a sense amplifier coupled to the memoryarray, or combinations thereof.
 20. A method, comprising: storing, usinga latch coupled to an accumulator and Boolean selection circuitryassociated with a memory array, a Boolean mask value in the accumulatoror in a sense amplifier coupled to the Boolean selection circuitry; andselectively disabling the Boolean selection circuitry responsive todetection of the Boolean mask value.
 21. A method, comprising: storing,using a latch coupled to an accumulator and Boolean selection circuitryassociated with a memory array, a Boolean mask value; discharging nodesof the accumulator to a ground reference potential; reducing an amountof contention between nodes of the accumulator by enabling a transistorcoupled to the Boolean selection circuitry and the accumulator; andselectively disabling the Boolean selection circuitry responsive todetection of the Boolean mask value.
 22. A method, comprising: storing,using a latch coupled to an accumulator and Boolean selection circuitryassociated with a memory array, a Boolean mask value; enabling a columnrepair signal line coupled to nodes of the accumulator to provide arepair capability to the accumulator, Boolean selection circuitry, asense amplifier coupled to the memory array, or combinations thereof;and selectively disabling the Boolean selection circuitry responsive todetection of the Boolean mask value.